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TA1322FN 2002-02-12 1 toshiba bipolar linear integrated circuit silicon monolithic TA1322FN down-converter ic with pll for satellite tuner the TA1322FN is a wideband down-converter which can operate at input frequency ranging from 850 mhz to 2200 mhz. intended primarily for use in satellite tuners, this ic includes an oscillator, a mixer, an if amplifier and a pll. the i 2 c bus data format is used as the data control format. the supply voltage of 5.0 v helps minimize the tuner?s power dissipation, while the compact 30-pin ssop package allows the tuner to be kept small. features supply voltage: 5.0 v (typ.) wide input frequency range low phase noise oscillator standard i 2 c bus format control 4-mhz (x?tal) buffer output pin reference oscillator input change-over switch [x?tal or external input] 33-v high-voltage tuning amplifier built-in built-in comparator (p4, p5, p7) bandswitch drive transistor (p0) [ibd = 40 ma (max)] selected if output port frequency step: 62.5 khz or 125 khz (for 4-mhz x?tal) 4-address setting via address selector power-on reset circuit 1/2 prescaler flat compact package: ssop30-p-300-0.65 (0.65-mm pitch) power-on reset operation conditions frequency step: 125 khz charge pump output current: 50 a counter data: all [0] band driver: off tuning amplifier: off if output operation: pin 19 is on note 1: this device can easily be damaged by high voltages or electrical fields. for this reason, please handle it with care. weight: 0.17 g (typ.) preliminar y
TA1322FN 2002-02-12 2 block diagram comparator i 2 c bus data interface band driver phase comparator programmable counter divider xo-sw 1/2 if-sw address 1 gnd1 2 v cc 1 3 osc-e 4 osc-b 5 gnd2 6 vt-ou t 7 nf 8 x?tal 9 v cc 2 10 xo buff ou t 11 gnd3 12 p4 13 p5 14 p7 15 scl in 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v cc 4 gnd7 rf in2 rf in1 gnd6 test xo sw gnd5 v cc 3 if out2 gnd4 if out1 adr set po out sda in/out 1/32 1/33
TA1322FN 2002-02-12 3 pin functions pin no. pin name function interface 1 gnd1 ground pin for oscillator circuit block 2 v cc 1 power supply pin for local oscillator circuit block 3 4 oscillator local oscillator circuit 5 gnd2 ground pin for oscillator circuit block 6 vt output 7 nf tuning voltage output pin with built-in tuning amplifier 8 reference input (4-mhz input) crystal oscillator input can be switched between x?tal oscillator and external input using pin 24 (xo switch). 9 v cc 2 power supply pin for pll circuit block 10 reference signal buffer output buffer output pin for reference signal 11 gnd3 ground pin for pll circuit block 2 4 3 gnd1 v cc 2 8 gnd3 1 k 5 k 5 k 1 k v cc 2 10 gnd3 5 k 5 k 6 v cc 2 gnd3 7 v cc 2 50
TA1322FN 2002-02-12 4 pin no. pin name function interface 12 p4 13 p5 14 p7 output can be controlled by setting the band switch data. the circuit configuration is open collector output. each pin has a built-in comparator. the status of the comparator can be checked read mode. 15 scl input input pin for i 2 c bus serial clock data 16 sda input/output input/output pin for i 2 c bus serial clock data 17 po output output can be controlled by setting band switch data. 18 adr set the address for hardware bit setting can be selected by applying voltage to this pin. 4 programmable address can be programmed. v cc 2 15 gnd3 1 k 100 v cc 2 16 gnd3 1 k 100 20 70 k gnd3 12, 13, 14 cmop v cc 2 17 gnd3 data i/f 12 k 12 k v cc 2 18 gnd3 50 k 150 k 100 1 k 100
TA1322FN 2002-02-12 5 pin no. pin name function interface 19 if output 1 21 if output 2 if output pin. output can be controlled by setting the band switch data (p6). if output impedance is 75 each other. when p6 data set 0, output pin is pin 19 (if output 1). when p6 data set 1, output pin is pin 21 (if output 2). 20 gnd4 ground pin for if amplifier circuit block 22 v cc 3 power supply pin for if amplifier circuit block 23 gnd5 ground pin for if amplifier circuit block 24 xo switch determines reference signal input. if connected to ground: x?tal oscillator. if open or connected to v cc 2: external input 25 test when test mode set, this pin can confirm x?tal divider signal and 1/2 counter signal. this pin can be used at open. 26 gnd6 ground pin for mixer circuit block 27 rf input1 28 rf input2 rf signal input pin input can be either balanced or unbalanced. 29 gnd7 ground pin for mixer circuit block 30 v cc 4 power supply pin for mixer circuit block v cc 3 gnd4, 5 19, 21 v cc 2 24 gnd3 25 k 25 k 1 k gnd7 27 28 3 k 3 k v cc 2 25 gnd3 25 k 100 k
TA1322FN 2002-02-12 6 absolute maximum ratings (ta 25c) parameter pin no. symbol rating unit 2 v cc 1 6 9 v cc 2 6 22 v cc 3 6 supply voltage 30 v cc 4 6 v tuning amplifier voltage 6 vbt 38 v power dissipation p d 1130 (note 2) mw operating temperature t opr 20 to 85 c storage temperature t stg 55 to 150 c note 2: 50 mm 50 mm 1.6 mm, 40% cu board if ta 25c, derate this value by 9.1 mw/c. recommended operating conditions pin no. symbol min typ. max unit 2 local oscillator block v cc 1 4.5 5.0 5.5 v 9 pll block v cc 2 4.5 5.0 5.5 v 22 if amplifier block v cc 3 4.5 5.0 5.5 v 30 mixer block v cc 4 4.5 5.0 5.5 v electrical characteristics dc characteristics (unless otherwise specified, v cc 1 v cc 2 v cc 3 v cc 4 5 v, ta 25c) when power on, counter data all [0], vbt off, cp0 0, band all [0], and if output operate pin 19. parameter symbol test circuit test condition min typ. max unit i cc 1 5.0 7.5 9.5 i cc 2 21.5 26.5 32.0 i cc 3 19.5 24.0 29.0 power supply current i cc 4 1 10.0 12.5 15.5 ma total i cc -total 56.0 70.0 86.0 ma
TA1322FN 2002-02-12 7 down-converter block ac characteristics (unless otherwise specified, v cc 1 v cc 2 v cc 3 v cc 4 5 v, ta 25c) parameter symbol test circuit test condition (note 4, note 5) min typ. max unit rf input frequency mfin 850 2200 mhz rf input level mpin 35 dbmw if output frequency afin 350 550 mhz if output impedance (note 3) azout single-end 75 local oscillator frequency lo 1300 2700 mhz frf 898 mhz 27.5 30.5 33.5 frf 1598 mhz 27 31 34 conversion gain (note 3) cg 3 frf 2198 mhz 24.5 29 32 db frf 898 mhz 9 10.5 frf 1598 mhz 9 11.5 noise figure (note 3) nf 4 frf 2198 mhz 11 13 db frf 898 mhz 6 8 frf 1598 mhz 6 8 if output power level (note 3) apsat 3 frf 2198 mhz 6 8 dbmw fd 898 mhz, fud 903 mhz 13 15 fd 1598 mhz, fud 1603 mhz 14 16 3 rd inter modulation (if output intercept point) (note 3) ip3 5 fd 2198 mhz, fud 2203 mhz 14 16 dbmw frf 898 mhz 2 frf 1598 mhz 2 conversion gain shift (note 3) cgs 3 frf 2198 mhz 2 db fosc 1300 mhz 5.5 fosc 2000 mhz 3.5 frequency shift (pll off) fb 3 fosc 2600 mhz 3.5 mhz fosc 1300 mhz 74 70 fosc 2000 mhz 75 71 phase noise (with 10-khz offset) pn 3 fosc 2600 mhz 74 70 dbc/ hz fosc 1300 mhz 36 33 fosc 2000 mhz 31.5 28 rf pin lo leak level lorf 3 fosc 2600 mhz 33 30 dbmw fosc 1300 mhz 21.5 15.5 fosc 2000 mhz 31 25 if pin lo leak level loif 3 fosc 2600 mhz 36 30.5 dbmw frf 898 mhz 30 36 frf 1598 mhz 30 36 if switch isolation ifiso 3 frf 2198 mhz 30 36 db note 3: if output frequency 402 mhz note 4: if output load 75 note 5: if output operate pin 21
TA1322FN 2002-02-12 8 pll block (unless otherwise specified, v cc 1 v cc 2 v cc 3 v cc 4 5 v, ta 25c) parameter symbol test circuit test condition min typ. max unit tuning amplifier output voltage (close) vt out 1 vbt 33 v, rl 33 k 0.3 33 v tuning amplifier maximum current ivt 1 vbt 33 v 3 ma x?tal negative resistance xtr 1 1 2.5 k x?tal operating frequency oscin 1 xo-sw:gnd (x?tal oscillator mode) [ndk (at-51), 4 mhz used] 3.2 4.5 mhz x?tal external input level xo extl 1 100 1000 mv p-p x?tal external input frequency x-ext 1 xo-sw: v cc 2 or open 2 6 mhz ratio setting range n 15-bit counter 1024 32767 logic input low voltage v il 1 0.3 1.5 v logic input high voltage v ih 1 sda and scl pins 3 v cc 2 0.3 v logic input current (low) i bsl 1 20 10 a logic input current (high) i bsh 1 sda and scl pins 10 20 a ack output voltage vack 1 isink 3 ma 0.4 v cp [0] 35 50 75 charge pump output current ichg 1 cp [1] 180 240 345 a band driver drive current ibd 1 p0 40 ma band driver voltage drop vbdsat 1 p0: ibd 40-ma drive 0.2 0.4 v comparator pin input voltage vcmp 1 ip4, ip5, ip7 0 6 v comparator pin low voltage vlcmp 1 ip4, ip5, ip7 0 1.5 v comparator pin high voltage vhcmp 1 ip4, ip5, ip7 2.7 6 v output port flow current ipin 2 p4, p5, p7 7 ma output port saturation voltage vpinsat 2 p4, p5, p7 (ipin 7 ma) 0.1 0.15 v output port leakage current iplk 1 p4, p5, p7 (vport 6 v) 10 a output port maximum voltage vport 1 p4, p5, p7 6 v xo buffer output level xo out 1 1-k , 10-pf load x?tal: ndk (at-51), 4 mhz used. 4-mhz level monitored on oscilloscope using fet probe (1 m , 1.9 pf). 350 500 mv p-p
TA1322FN 2002-02-12 9 bus line characteristics parameter symbol test circuit test condition min typ. max unit scl clock frequency fscl 0 100 khz bus free time between a stop and start conditions t buf 4.7 s hold time for repeated start condition t hd ; sta 4 s scl clock low period t low 4.7 s scl clock high period t high 4 s set-up time for repeated start condition f su ; sta 4.7 s data hold time t hd ; dat 0 s data set-up time t su ; dat 250 ns rise time for sda and scl signals tr 1000 ns fall time for sda and scl signals tf 300 ns set-up time for stop condition tsu; sto please refer to data timing chart. 4 s t hd ; sta tsu; sto sda scl t buf t low tr tf t hd ; sta t hd ; dat t high t su ; dat t su ; sta p s sr p figure 1 i 2 c bus data timing chart (rising-edge timing)
TA1322FN 2002-02-12 10 test conditions (1) conversion gain rf input level 40dbmw (2) noise figure nf meter direct-reading value (dsb measurement) (3) if output power level measure maximum if output level. (4) 3rd inter modulation fd (fd input level 40dbmw) fud fd 5 mhz (fud input level 40dbmw) calculate if output intercept point as follows: ip3 s/(n 1) p [dbmw] s: suppression level n: 3 p: if output level (5) conversion gain shift conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges v cc 5 v to 4.5 v or v cc 5 v to 5.5 v. (6) frequency shift (pll off) frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges v cc 1 5 v to 4.5 v or v cc 1 5 v to 5.5 v. (7) phase noise (offset 10 khz) measure phase noise at 10-khz offset. (8) rf pin local-leak level measure worst-case local-leak level for rf pin (with if output pin open). (9) if pin local-leak level measure worst-case local-leak level for if pin (with rf input pins shorted using 50- resistor, and not measure if output pin open). (10) if switch isolation rf input level 40dbmw measure selected if output pin?s level, and not selected if output pin?s level. ifiso = |(selected if output pin?s level ) (not selected if output pin?s level)| not selected if output pin shorts using 50 resistor.
TA1322FN 2002-02-12 11 pll block --i 2 c bus communications control-- the TA1322FN conforms to standard mode i 2 c bus format. i 2 c bus mode allows two-way bus communication using write mode (for receiving data) and read mode (for processing status data). write mode or read mode can be selected by setting the least significant bit (r/w bit) of the address byte. if the least significant address bit is set to 0, write mode is selected; if it is set to 1, read mode is selected. address can be set using the hardware bits. 4 programmable address can be programmed. using this setting, multiple frequency synthesizers can be used on the same i 2 c bus line. the address for the hardware bit setting can be selected by applying voltage to the address setting pin (adr-pin 18). the address is selected according to the setting of these bits. during acknowledgment of receipt of a valid address byte, the serial data (sda) line is low. if write mode is currently selected, when the data byte is programmed, the serial data (sda) line will be low during the next acknowledgment. a) write mode (setting command) when write mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte 4 holds the divider ratio setting and function setting data; and byte 5 holds output port data. data is latched and transferred at the end of byte 3, byte 4 and byte 5. byte 2 and byte 3 are latched and transferred as a byte pair. once a valid address has been received and acknowledged, the data type can be determined by reading the first bit of the next byte. that is, if the first bit is 0, the data is frequency data; if it is 1, the data is function-setting or band output data. additional data can be input without the need to transmit the address data again until the i 2 c bus stop condition is detected (e.g. a frequency sweep using additional frequency data is possible). if a data transmission is aborted, data programmed before the abort remains valid. [[byte 1]] the address data for byte 1 can be set using the hardware bit. the hardware bit can be set by applying a voltage to the address-setting pin (adr: pin 18). [[byte 2, byte 3]] byte 2, byte 3 control the 15-bit programmable counter ratio and are stored in the 15-bit shift register together with frequency setting counter data. the program frequency can be calculated using the following formula: fosc 2 fr n fosc: program frequency fr: phase comparator reference frequency n: counter total divider ratio fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (the control byte). (fr x?tal oscillator frequency/reference divider ratio) the reference frequency divider ratio can be set to 1/64 or 1/128. when a 4-mhz crystal oscillator is used, fr 62.5 khz or 31.25 khz. the respective step frequencies are 125 khz and 62.5 khz. [[byte 4]] byte 4 is a control byte used to set function. bit 2 (cp) controls the output current of the charge-pump circuit. when bit 2 is set to [0], the output current is set to 50
a; when set to [1], 240
a. bit 3 (t1) is used to set the test mode. when bit 3 is set to [0], normal mode; when set to [1], test mode. bit 4 (t0) is used to set the charge pump. when bit 4 is set to [0], charge pump is on (normal used); when set to [1], charge pump is off. bit 5 (ts2) and bit 6 (ts1) used to set the test mode. they are used to set the charge pump test, phase comparator reference signal output, and 1/2 counter divider ratios. bit 7 (ts0) is used to set the x?tal reference frequency divider ratio. when bit 7 is set to [0], 1/128 (frequency step is 62.5 khz); when set to [1], 1/64 (frequency step is 125 khz). bit 8 (os) is used to set the charge pump drive amplifier output setting. when bit 8 is set to [0],
TA1322FN 2002-02-12 12 the output is on (normal mode); when set to [1], the output is off. [[byte 5]] byte 5 can be used to set control the output port. bit 1 (p7), bit 3 (p5) and bit 4 (p4) are used to control output port p7, p5 and p4. bit 2 (p6) is used to control change if output port. when bit 2 is set to [0], if output 1 (pin 19) is on; when set to [1], if output 1 (pin 21) is on. bit 8 (p0) is used to control band output port (p0). when bit 8 is set to [0], p0 is off; when set to [1], p0 is on. (p0) output port can be driven at less than 40 ma. b) read mode (status request) when read mode is set, power-on reset operation status, phase comparator lock detector output status, comparator input voltage status are output to the master device. bit 1 (por) indicates the power-on reset operation status. when the power supply of v cc 2 stops, bit is set to [1]. the condition for reset to [0], voltage supplied to v cc 2 is 3 v or higher, transmission is requested in read mode, and the status is output. (when v cc 2 is turned on, bit 1 is also set to [1].) bit 2 (fl) indicates the phase comparator lock status. when locked, [1] is output; when unlocked, [0] is output. bit 3 (ip7), bit 4 (ip5) and bit 5 (ip4) indicate the input comparator status. high level status is output [1], low level status is output is [0]. when voltage applied from 0 v to 1.5 v, output is [0]. when from 2.7 v to 6 v, output is [1]. data format a) write mode msb lsb 1 address byte 1 1 0 0 0 ma1 ma0 r/w 0ack 2 divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 ack 3 divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 ack (l) 4 control byte 1 cp t1 t0 ts2 ts1 ts0 os ack (l) 5 band sw byte p7 p6 p5 p4

p0 ack (l) : don?t care ack: acknowledged (l): latch and transfer timing b) read mode msb lsb 1 address byte 1 1 0 0 0 ma1 ma0 r/w 1ack 2 status byte por fl ip7 ip5 ip4 1 1 1 ack: acknowledged
TA1322FN 2002-02-12 13 data specifications ma1 and ma0: programmable hardware address bits ma1 ma0 voltage applied to address pin 0 0 0 to 0.1v cc 2 0 1 open or 0 to v cc 2 1 0 0.4v cc 2 to 0.6v cc 2 1 1 0.9v cc 2 to v cc 2 n14-n0: programmable counter data cp: charge pump output current setting [0]: 50
a (typ.) [1]: 240
a (typ.) t1: test mode setting [0]: normal mode [1]: test mode t0: charge pump setting [0]: charge pump is on (normal mode) [1]: charge pump is off ts0: x?tal reference frequency divider ratio select bits. ts0 divider ratio step frequency fr 0 1/128 62.5 khz 31.25 khz 1 1/64 125 khz 62.5 khz t1, ts2, ts1, ts0: test mode characteristics t1 ts2 ts1 ts0 divider ratio notes normal operation 0

0 1/128 normal operation 0

1 1/64 sink 1 1 0 0 1/128 charge pump source 1 1 0 1 1/64 output port off 1 1 1 0 1/128 p7, p5, p4 off phase comparator test 1 1 1 1 1/64 sda: comparative signal input scl: reference signal input 1 0 0 0 1/128 x?tal divider counter output 1 0 0 1 1/64 output to pin 25 (test) 1 0 1 0 1/128 1/2 counter divider output 1 0 1 1 1/64 output to pin 25 (test) : don?t care note 5: when test mode, os 0 (tuning on) is necessary. when testing the counter divider output, programmable counter data input is necessary.
TA1322FN 2002-02-12 14 os: tuning amplifier control setting [0]: tuning amplifier on (normal operation) [1]: tuning amplifier off p4, p5, p7: output port [0]: off [1]: on p6: if output port switchover p6 output port 0 if output 1 (pin 19) is on 1 if output 2 (pin 21) is on p0: band output [0]: off [1]: on this can be driven at less than 40 ma. por: power-on reset flag [0]: normal operation [1]: reset operation fl: lock detect flag [0]: unlocked [1]: locked ip4, ip5, ip7: comparator output [0]: supply voltage is from 0 v to 1.5 v [1]: supply voltage is from 2.7 v to 6 v xo-sw: reference signal input changeover pin 24 input method gnd x?tal v cc 2 or open external input
TA1322FN 2002-02-12 15 test circuit 1 dc characteristics x?tal: ndk (at-51), 4 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 comparator i 2 c bus data interface band driver phase comparator programmable counter divider xo-sw 1/2 0.01 f v cc 1 (5 v) nf nc nc nc i cc 1 p5 p4 scl p7 4 mhz out v cc 2 (5 v) 1 nf 10 pf 1 k 0.01 f a i cc 2 a ext.in 1 nf 22 pf * x?tal sda test v cc 3 (5 v) v nc a i cc 3 0.01 f v cc 4 (5 v) a 0.01 f i cc 4 1 nf 1 nf vbd sat ibd xo-sw v cc 2/open v cc 2/open: extenal input gnd: x?tal adr set nc a 390 if-sw address 390 15 1/32 1/33
TA1322FN 2002-02-12 16 test circuit 2 dc characteristics measurement for ?output port flow current? and ?output port saturation voltage?. test circuit 3 ac characteristics v i pin 12, 13, 14 a v pinsat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 comparator i 2 c bus data interface band driver phase comparator programmable counter divider xo-sw 1/2 p5 p4 scl p7 test 0.1 f 0.1 f 1 nf xo-sw v cc 2/open v cc 2/open: extenal input gnd: x?tal if-sw address 390 15 1 nf rf in 1 nf sda po out adr set if out 1 if out 2 1 nf 390 1 nf 4 mhz out 1 nf 0.1 f l 47 pf 22 pf x?tal 4.7 nf 13 k 0.1 f 5 pf 10 k 4.7 k 4.7 nf 10 k 1t379 1t379 1 nf 47 k 33 v 0.1 f 5 v 1/32 1/33
TA1322FN 2002-02-12 17 test circuit 4 measuring noise figure test circuit 5 measuring 3 rd inter modulation 28 dut 75 -50 impedance transformer noise figure meter out in if output pin noise source fud spectrum analyzer fd signal generator 2 signal generator 1 28 dut in 75 -50 impedance transformer if output pin
TA1322FN 2002-02-12 18 i 2 c-bus control summary the bus control format of TA1322FN conforms to the philips i 2 c-bus control format. data transmission format s: start condition p: stop condition a: acknowledge (1) start/stop condition (2) bit transfer (3) acknowledge serial data serial clock serial data can be changed. serial data unchanged. serial data serial clock s start condition p stop condition 7 bits 8 bits 8 bits msb msb msb s slave address 0 a sub address a data a p high-impedance serial data from master device s 8 1 serial clock from slave serial clock from master device 9 high-impedance
TA1322FN 2002-02-12 19 (4) slave address a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 0 0 * * 0 purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent tights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. handling precautions 1. the device should not be inserted into or removed from the test jig while a voltage is being applied to it: otherwise the device may be degraded or break down. also, do not abruptly increase or decrease the power supply to the device (see figure 1). overshoot or chattering in the power supply may cause the ic to be degraded. to avoid this, filters should be placed on the power supply line. 2. the peripheral circuits described in this datasheet are given only as system examples for evaluating the device?s performance. toshiba intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. please note that the high-frequency characteristics of the device may vary depending on the external components, the mounting method and other factors relating to the application design. therefore, the evaluation of the characteristics of application circuits is the responsibility of the designer. toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer?s application design. 3. in order to better understand the quality and reliability of toshiba semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest semiconductor reliability handbook (integrated circuits) published by toshiba semiconductor company. this handbook can also be viewed on-line at the following url: . 1 ms time 10% 90% 6 v ( v cc 1, v cc 2, v cc 3, v cc 4) 38 v (vbt) supply voltage figure 1
TA1322FN 2002-02-12 20 package dimensions weight: 0.17 g (typ.)
TA1322FN 2002-02-12 21 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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